The present invention relates to a pulse generator for generating a pulse train which is used for sampling character data of a teletext (or videotext) system.
In a teletext system, a broadcasting station transmits a teletext signal being formed of a television broadcasting signal (video signal) and character data signal which is superposed on the video signal, and at the receiver side the character data signal is extracted from the teletext signal and the extracted signal is processed, thereby displaying character information on the CRT screen.
FIG. 1A shows a main part of the teletext signal. Character data signal D is interposed or superposed on one or more horizontal periods among the 10th to 20th horizontal periods of the vertical blanking interval. FIG. 1B shows the format of character data signal D. Signal D includes a header section A1 containing a clock run-in signal CR and framing code FC, and data section A2 in which actual character data etc., is inserted. The video signal also includes a vertical sync signal SV, horizontal sync signal SH and color burst signal SB. FIG. 1C shows the clock run-in signal CR in detail. Signal CR consists of 8 clock pulses located at the leading portion of header section A1. Signal CR serves as a reference phase of character data signal D. Various data succeeding the clock run-in signal CR is transmitted with the same bit rate as the bit rate of this signal CR. The frequency of signal CR which defines the transfer rate is selected to 4/5 fsc (fsc being color subcarrier frequency). This 4/5 fsc is a half of the transfer rate frequency (8/5 fsc) of the succeeding various data.
On the receiving side, a sampling pulse SP with 8/5 fsc being synchronized to the signal CR is generated, and character data signal D is sampled by the pulse SP. A pulse G shown in FIG. 1D is in-phase with the signal D superposed on a horizontal period. Pulse G may be called "a gate pulse". A circuit for processing character data signal D provided in the receiver side samples character data etc., during the period wherein the pulse G is generated. Then, this processing circuit transfers the sampled data to a buffer memory. At this time a framing code in character data signal D is compared with a pre-entered framing code in the memory of the processing circuit, and only when the two framing codes coincide with each other, succeeding data (sampled data) is written in the buffer memory. Data written in the buffer memory is signal-processed to obtain a character signal, and the obtained signal is supplied to a CRT for character display.
There are two different systems for obtaining the sampling pulse SP which should be synchronized to a signal to be sampled. They are an analog system and digital system. Where an analog system is utilized to sample the character data signal D, a so-called "ringing system" may be employed, wherein the oscillation of an oscillator for generating the sampling pulse is synchronized to the clock run-in signal CR as in the case of synchronizing system of a color synchronization circuit in a TV receiver.
Where a digital system is utilized to sample the character data signal D, the clock run-in signal CR is sampled by a signal having a higher frequency than the frequency of signal CR, in order to detect the phase difference between the higher frequency signal and the signal CR. Then, the oscillation of an oscillator for producing the sampling pulse is controlled according to the detected result.
Problems arise where the analog system is employed. In general the character data signal D is provided only once in each field. From this, the circuit design for obtaining reliable pull-in of synchronizing is very difficult, so that the sampling pulse SP with high precision of phase cannot be obtained. Even if several character data signals are provided in one field, reliable pull-in of synchronizing, and hence a high-phase-precision sampling pulse, also cannot be obtained. This is because the phase of character data signal D varies for each horizontal scanning period in which the signal D is inserted.
Where the digital system is employed, there are the following problems. In order to keep the phase deviation of sampling pulse SP within 20 ns, for example, a signal having 8 times as high as the frequency of clock run-in signal CR is required. As mentioned before, the frequency of clock run-in signal CR is 4/5 fsc, which is very high. Therefore, a circuit dealing with signals having 8 times as high (32/5 fsc) must be adopted by circuit elements of the high speed type so as to meet the requirement of high speed operation. However, this causes a substantial increase in the manufacturing cost.